This invention relates generally to design of integrated circuits such as processors and, more specifically, relates to environments in which such design is carried out.
Much process of modern microarchitecture design for integrated circuits such as processors has been—to a large degree—automated. Individual or teams of designers develop modules that perform sets of functions. Each module forms one part of the design. These modules are implemented according to the specification of logic, simulated for functional correctness and performance evaluation, and finally synthesized into integrated circuits in a design environment. Modules may also be called macros or blocks.
The modules can be implemented in a hardware description language such as VHDL, Verilog, System Verilog, SystemC, etc. For instance, in SystemC, a module can be mapped to one or multiple of container classes of functionality with state, behavior, and structure for hierarchical connectivity, called sc_module. Modules may be abstract so as to capture partial logic or miss out low-level details, and thus not ready for synthesis yet. Or, they may be detailed and thus synthesizable. Here, synthesis is a process to convert design description eventually to a “netlist” or other information that is used to manufacture an integrated circuit.
Typically, a design starts at a high level, where various functions are split across several modules. Ideally, each module is as independently designed and evaluated as possible, in order to parallelize design efforts. However, traditional design environments do not support such parallelized design productivity, thereby reducing the ability for the designers to evaluate their modules without other modules. This is particularly true for complex, pipelined logic, such as processor designs, where individual modules affect different parts of the pipeline. For instance, a branch prediction module may affect and interact with multiple parts of the pipeline such as instruction fetch and branch execution modules. Even if each module is designed independently, the overall design may not be fully simulated or synthesized until late in the process, when all the other modules interacting with it are completed. Not only does this limitation prolong development time but it also prevents the designers from improving their design in the meantime.